Area efficient time-shared FIR filters in nanoscale CMOS

Parallelism has been used in the past as a high level architectural transformation for reducing the dynamic power consumption of FIR filters. However increasing the level of parallelism incurs an area penalty. In nanoscale CMOS circuits, leakage power is emerging as the dominant mode of power consumption. Leakage power is strongly correlated to the area and the total number of leaking transistors. This requires the classical area vs. power tradeoffs to be revisited. In addition to reducing the dynamic power, the increased timing slacks in the circuits with a higher degree of parallelism, can also be exploited for implementing the circuit using slower, low-leakage transistors. Hence the efficiency with which an architecture can trade area for increased timing slack is an important consideration for low power design in nanoscale CMOS. The current work shows that the algorithmic strength reduction achieved by fast filter algorithms (FFAs) can be used to design a class of time-shared FIR filters which are more area efficient than traditional structures, under specific conditions.