Title :
Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling
Author :
Fraguela, Basilio B. ; Voronenko, Yevgen ; Puschel, Markus
Author_Institution :
Depto. de Electron. e Sist., Univ. da Coruna, Corua, Spain
Abstract :
Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier transforms (FFTs) present a far more complex search space consisting of many thousands of different implementations with very different complex access patterns and nesting and code structures. As a results, some of the best available FFT implementations use heuristic search based on runtime measurements. In this paper we present the first analytical model that can successfully replace the measurement in this search on modern platforms. The model includes many details of the platform´s memory system including the TLBs, and, for the first time, physically addressed caches and hardware prefetching. The effect, as we show, is a dramatically reduced search time to find the best FFT without significant loss in performance. Even though our model is adapted to the FFT in this paper, its underlying structure should be applicable for a much larger set of code structures and hence is a candidate for iterative compilation.
Keywords :
automatic programming; cache storage; discrete Fourier transforms; program compilers; program control structures; Spiral program generator; analytical modeling; cache prefetching; code structures; discrete Fourier transforms; fast Fourier transforms; hardware prefetching; heuristic search; iterative compilation; loop nests; memory system; runtime measurements; search space; tile sizes; Analytical models; Context modeling; Discrete Fourier transforms; Flexible printed circuits; Hardware; Iterative algorithms; Libraries; Runtime; Spirals; Tiles; FFT; automatic performance tuning; discrete Fourier transform; high-performance computing; library generators; model-driven optimization; program optimization;
Conference_Titel :
Parallel Architectures and Compilation Techniques, 2009. PACT '09. 18th International Conference on
Conference_Location :
Raleigh, NC
Print_ISBN :
978-0-7695-3771-9
DOI :
10.1109/PACT.2009.11