DocumentCode :
3457042
Title :
Region Based Structure Layout Optimization by Selective Data Copying
Author :
Mannarswamy, Sandya S. ; Govindarajan, R. ; Surendran, Rishi
Author_Institution :
Hewlett-Packard, Bangalore, India
fYear :
2009
fDate :
12-16 Sept. 2009
Firstpage :
338
Lastpage :
347
Abstract :
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to modify an applicationpsilas data layout to improve cache locality and cache reuse. Whole program structure layout [WPSL] transformations can significantly increase the spatial locality of data and reduce the runtime of programs that use link-based data structures, by increasing the cache line utilization. However, in production compilers WPSL transformations do not realize the entire performance potential possible due to a number of factors. Structure layout decisions made on the basis of whole program aggregated affinity/hotness of structure fields, can be sub optimal for local code regions. WPSL is also restricted in applicability in production compilers for type unsafe languages like C/C++ due to the extensive legality checks and field sensitive pointer analysis required over the entire application. In order to overcome the issues associated with WPSL, we propose region based structure layout (RBSL) optimization framework, using selective data copying. We describe our RBSL framework, implemented in the production compiler for C/C++ on HP-UX IA-64. We show that acting in complement to the existing and mature WPSL transformation framework in our compiler, RBSL improves application performance in pointer intensive SPEC benchmarks ranging from 3% to 28% over WPSL.
Keywords :
data structures; program compilers; C/C++; production compiler; region based structure layout optimization; selective data copying; whole program structure layout; Data structures; Frequency; Humans; Inspection; Optimizing compilers; Parallel architectures; Performance analysis; Production; Program processors; Runtime; cache locality; compiler; structure layout optimization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures and Compilation Techniques, 2009. PACT '09. 18th International Conference on
Conference_Location :
Raleigh, NC
ISSN :
1089-795X
Print_ISBN :
978-0-7695-3771-9
Type :
conf
DOI :
10.1109/PACT.2009.43
Filename :
5260527
Link To Document :
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