DocumentCode
3457210
Title
A 12-bit 10-MHz BiCMOS comparator
Author
Razavi, Behzad ; Wooley, Bruce A.
Author_Institution
Center for Integrated Syst., Stanford Univ., CA, USA
fYear
1991
fDate
9-10 Sep 1991
Firstpage
289
Lastpage
292
Abstract
The design of a self-calibrating BiCMOS comparator is presented. The circuit uses a preamplifier followed by two regenerative states to achieve an input offset of 200 μV at a conversion rate of 10 MHz. The comparator has an input range of 3 V and dissipates 1.7 mW from a 5-V supply. The comparator was designed for use in 12-b half-flash analog-to-digital converter systems and performs offset cancellation during overdrive recovery in every cycle, thereby eliminating flicker noise
Keywords
BIMOS integrated circuits; analogue-digital conversion; calibration; comparators (circuits); linear integrated circuits; 1.7 mW; 10 MHz; 3 V; 5 V; BiCMOS comparator; flicker noise elimination; half-flash ADC; offset cancellation; overdrive recovery; preamplifier; regenerative states; self-calibrating; BiCMOS integrated circuits; CMOS technology; Calibration; Capacitors; Dynamic voltage scaling; Grounding; Latches; Power dissipation; Preamplifiers; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar Circuits and Technology Meeting, 1991., Proceedings of the 1991
Conference_Location
Minneapolis, MN
Print_ISBN
0-7803-0103-X
Type
conf
DOI
10.1109/BIPOL.1991.161005
Filename
161005
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