DocumentCode
3457375
Title
A technique for fault detection in C-testable orthogonal iterative arrays
Author
Huang, W.-K. ; Lombardi, F.
Author_Institution
Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
fYear
1988
fDate
11-14 Apr 1988
Firstpage
203
Lastpage
212
Abstract
The authors present an approach to C-testability of orthogonal iterative arrays. C-testability is defined by those criteria which characterize the complexity of the testing process as independent of the dimensions of the array and of the erroneous states of the cells. The proposed approach is based on a cellular automata characterization under a single-faulty-cell assumption. This characterization analyzes the state transition table of a basic cell and adds new states to it. These new states are used to reproduce internally to the array the test input and propagate the faulty state to the output pins of a chip. This process is analyzed exhaustively. The characteristics of the additional states are presented. The conditions of C-testability are fully proved. Complexity of the testing process (number of test vectors) is discussed. It is proved that the proposed approach has a lower complexity than previously published work
Keywords
cellular arrays; fault tolerant computing; integrated circuit testing; C-testability; C-testable orthogonal iterative arrays; cellular automata characterization; chip; complexity; fault detection; output pins; single-faulty-cell assumption; state transition table; test vectors; testing process; Array signal processing; Electrical fault detection; Fault detection; Iterative methods; Manufacturing; Pins; Sequential analysis; Testing; Very large scale integration; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
CompEuro '88. 'Design: Concepts, Methods and Tools'
Conference_Location
Brussels
Print_ISBN
0-8186-0834-X
Type
conf
DOI
10.1109/CMPEUR.1988.4953
Filename
4953
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