Analysis of power supply noise mitigation circuits

Author

Charania, Tasreen ; Chuang, P. ; Opal, Ajoy ; Sachdev, Manoj

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada

fYear

2011

fDate

8-11 May 2011

Abstract

Power supply noise has become an increasing concern for circuit designers with the recent advances in technology. As a result there has been an introduction of active supply noise mitigation circuits in addition to the currently used passive bypass/decoupling capacitors for on-chip noise suppression. This paper proposes figures of merit for characterizing the various emerging mitigation circuits as well as provides a theoretical and practical analysis of a switched capacitor based active mitigation technique for the CMOS 65 nm technology node.

Keywords

CMOS integrated circuits; capacitors; interference suppression; power supply circuits; switched capacitor networks; CMOS technology node; active supply noise mitigation circuits; circuit designers; on-chip noise suppression; passive bypass/decoupling capacitors; power supply circuits; power supply noise; size 65 nm; switched capacitor; Capacitance; Capacitors; Integrated circuit modeling; Noise; RLC circuits; Switches; Switching circuits; CMOS 65 nm; decoupling capacitor; noise mitigation; noise suppression; power supply noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering (CCECE), 2011 24th Canadian Conference on

Conference_Location

Niagara Falls, ON

ISSN

0840-7789

Print_ISBN

978-1-4244-9788-1

Electronic_ISBN

0840-7789

Type

conf

DOI

10.1109/CCECE.2011.6030663

Filename

6030663