Title :
Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs
Author :
Barik, Rajkishore ; Sarkar, Vivek
Author_Institution :
Dept. of Comput. Sci., Rice Univ., Houston, TX, USA
Abstract :
Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is to replace a memory access, such as a read of an object field or an array element, by a read of a compiler-generated temporary that can be allocated in faster and more energy-efficient storage structures such as registers and local memories (scratchpads). Unfortunately, current just-in-time and dynamic compilers perform load elimination only in limited situations. In particular, they usually make worst-case assumptions about potential side effects arising from parallel constructs and method calls. These two constraints interact with each other since parallel constructs are usually translated to low-level runtime library calls. In this paper, we introduce an interprocedural load elimination algorithm suitable for use in dynamic optimization of parallel programs. The main contributions of the paper include: a) an algorithm for load elimination in the presence of three core parallel constructs -- async, finish, and isolated, b) efficient side-effect analysis for method calls, c) extended side-effect analysis for parallel constructs using an isolation consistency memory model, and d) performance results to study the impact of load elimination on a set of standard benchmarks using an implementation of the algorithm in Jikes RVM for optimizing programs written in a subset of the X10 v1.5 language. Our performance results show decreases in dynamic counts for getfield operations of up to 99.99%, and performance improvements of up to 1.76times on 1 core, and 1.39times on 16 cores, when comparing the algorithm in this paper with the load elimination algorithm available in Jikes RVM.
Keywords :
optimising compilers; parallel programming; storage management; compiler transformation; dynamic optimization; interprocedural load elimination; isolation consistency memory model; parallel program; storage structure; Algorithm design and analysis; Dynamic compiler; Energy efficiency; Energy storage; Hardware; Optimization methods; Parallel processing; Performance analysis; Registers; Runtime library; Load elimination; dynamic compilation; dynamic optimization; memory model; parallel program; scalar replacement;
Conference_Titel :
Parallel Architectures and Compilation Techniques, 2009. PACT '09. 18th International Conference on
Conference_Location :
Raleigh, NC
Print_ISBN :
978-0-7695-3771-9
DOI :
10.1109/PACT.2009.32