Synchronous design of 8259 Programmable Interrupt Controller

This paper presents the design of a synchronous 8259 Programmable Interrupt Controller (PIC) that is functionally compatible with the existing asynchronous design of 8259 PIC. The main objective is to reduce the design review efforts along the process technology migration. It also serves as the solutions for the disadvantages and potential hazards inherited in the asynchronous 8259 PIC such as timing loops, race conditions, undetectable signal pulse width and glitches. It is a clock gated synchronous design with only flip flops as the memory elements in it. This synchronous design is implemented using a standard-cell based 32 nm CMOS process. Pre-layout simulation results demonstrate an equivalent interrupt handling mechanism with approximate increase of 0.3% in total gate count and 12.2% in area correspondingly compared to the existing design. Although there is increment of 4.7uW in total dynamic power consumption, but the range of `uW´ is acceptable. It can be explained by the higher switching activity of the gated clock signal in the synchronous 8259 PIC compared to the handshaking signal in the asynchronous counterpart.