A novel 36 bit single fault tolerant multiplier using 5 bit moduli

Author

Radhakrishnan, D. ; Preethy, A.P.

Author_Institution

Div. of Comput. Eng., Nanyang Technol. Inst.

Volume

1

fYear

1998

fDate

1998

Firstpage

128

Abstract

A large range integer multiplier using a set of small moduli is presented. The multiplier speed is increased by applying logarithmic principles. This is achieved by selecting prime and powers of prime moduli for the residue number system, and by using index calculus techniques on all moduli. The use of powers of prime moduli was instrumental in providing additional moduli needed for single error correction while keeping the size of each individual moduli small

Keywords

Galois fields; calculus; error correction; multiplying circuits; residue number systems; 36 bit; 5 bit; Galois fields; index calculus; integer multiplication; large range integer multiplier; logarithmic principles; multiplier speed; prime moduli; residue number system; single error correction; single fault tolerant multiplier; small moduli size; Arithmetic; Calculus; Error correction; Fault tolerance; Finite impulse response filter; Instruments; Power engineering and energy; Power engineering computing; Registers; Variable speed drives;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '98. 1998 IEEE Region 10 International Conference on Global Connectivity in Energy, Computer, Communication and Control

Conference_Location

New Delhi

Print_ISBN

0-7803-4886-9

Type

conf

DOI

10.1109/TENCON.1998.797095

Filename

797095