A noise and signal integrity verification flow for hierarchical design

Hierarchical design spans the complete framework of a design flow from RTL, synthesis, place and route, timing closure and various other analyses before signoff. Finer geometries and increasing interconnect density however have resulted signal integrity becoming the key issue for Deep Sub-Micron design. This paper discusses how to analyze, avoid and suggest a proper solution to deal with signal integrity effect in a hierarchical design. The intention is to ensure that a complex design can be delivered to the market with accurate, fast and trusted analysis and sign-off solution. Main proposed approach is to analyze a 45nm process technology hierarchical design using Primetime-SI. Signal integrity effects in the design are explored thoroughly to guarantee any recommendation made to reduce and repair the signal integrity effects is suitable and appropriate. Case study presented demonstrates the proposed methodology has provided valuable and useful perimeter to overcome signal integrity caveats in hierarchical design.