Title :
A Dividing Ratio Changeable Digital PLL Using VCO as Base Clock Source
Author :
Yahara, Mitsutoshi ; Fujimoto, Kuniaki ; Hirose, Takanori ; Sasaki, Hirofumi
Author_Institution :
Fukuoka Junior Coll., Tokai Univ., Munakata, Japan
Abstract :
In this paper, the dividing ratio changeable digital phase locked loop (DCPLL) using the VCO as the base clock source is proposed. In this circuit, the ratio of output jitter is not greatly influenced for the input signal. Also, the lock-in range can be widely compared with the conventional method.
Keywords :
digital phase locked loops; jitter; voltage-controlled oscillators; VCO; base clock source; dividing ratio changeable digital PLL; input signal; lock-in range; output jitter ratio; phase locked loop; voltage controlled oscillator; Automatic control; Clocks; Counting circuits; Frequency conversion; Jitter; Phase control; Phase locked loops; Pulse circuits; Space vector pulse width modulation; Voltage-controlled oscillators;
Conference_Titel :
Innovative Computing, Information and Control (ICICIC), 2009 Fourth International Conference on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4244-5543-0
DOI :
10.1109/ICICIC.2009.9
