A wide range (550-700 MHz) monolithic timing recovery circuit

A retiming technology has been developed which enables timing recovery of a pseudorandom (2²³-1) data sequence to be accomplished in a single IC chip at high bit rates (550-700 Mb/s). The retiming technology incorporates a digital bang-bang method to adjust the onboard IC ring oscillator to the rate of the incoming data. Both timing extraction and data regeneration are accomplished on the same chip. The retiming IC was realized in a high-speed silicon bipolar process. For a 622-Mb/s input rate, the recovered timing has a jitter of less than 2 degrees phase. The technology provides a recovered timing lock in less than 2 ms. The performance of the chip under a variety of conditions is presented