Title :
CMOS downscaling and process induced damages
Author_Institution :
Frontier Collaborative Res. Center, Tokyo Inst. of Technol., Yokohama, Japan
Abstract :
The progress of electronic circuits has been made by the downsizing of its components such as MOSFETs. Recently, CMOS downsizing has been accelerated very aggressively, and even transistor operation of a 6 nm gate length p-channel MOSFET has been reported. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into the market or not. In this paper, past and expected future trends of CMOS downscaling are described including the issue of process-induced damage.
Keywords :
CMOS integrated circuits; MOSFET; VLSI; integrated circuit reliability; integrated circuit yield; nanotechnology; radiation effects; 6 to 10 nm; CMOS downscaling; CMOS downsizing; future trends; large scale integrated circuits; p-channel MOSFET; process induced damage; small-geometry MOSFETs; sub-10 nm CMOS LSIs; transistor operation; Acceleration; CMOS integrated circuits; CMOS process; CMOS technology; Consumer electronics; Electronic circuits; Integrated circuit technology; Large scale integration; MOSFETs; Silicon;
Conference_Titel :
Plasma- and Process-Induced Damage, 2003 8th International Symposium
Print_ISBN :
0-7803-7747-8
DOI :
10.1109/PPID.2003.1199718
