Development of a CMOS time memory cell VLSI and a CAMAC module with 0.5 ns resolution

Author

Arai, Y. ; Ikeno, M. ; Matsumura, T.

Author_Institution

Nat. Lab. for High Energy Phys., KEK, Ibaraki, Japan

fYear

1991

fDate

2-9 Nov. 1991

Firstpage

691

Abstract

A CMOS time-to-digital converter chip, the time memory cell (TMC), for high-rate wire chamber application has been developed. The chip has a timing resolution of 0.52 ns, dissipates only 7 mW/channel, and contains four channels in a chip. Each channel has 1024 memory locations which act as a buffer 1- mu s deep. The chip was fabricated in a 0.8- mu m CMOS process and is 5.0 mm by 5.6 mm. A CAMAC module with 32 input channels was developed using the TMC chip. This module is designed to operate in both common start and common stop modes. The circuit of the module and test results are described.<>

Keywords

CAMAC; CMOS integrated circuits; VLSI; nuclear electronics; physics computing; proportional counters; 0.5 ns; CAMAC module; CMOS time memory cell VLSI; common start; common stop modes; high-rate wire chamber application; input channels; memory locations; module; test results; time-to-digital converter chip; timing resolution; CAMAC; CMOS process; CMOS technology; Circuit testing; Clocks; Delay effects; Energy resolution; Laboratories; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium and Medical Imaging Conference, 1991., Conference Record of the 1991 IEEE

Conference_Location

Santa Fe, NM, USA

Print_ISBN

0-7803-0513-2

Type

conf

DOI

10.1109/NSSMIC.1991.259027

Filename

259027