Implementation of IEEE 802.15.4-based OQPSK-pulse-shaping block on FPGA

This paper describes implementation of an offset quadrature phase shift keying (OQPSK)-pulse-shaping block as a part of digital transmitter. The implementation is based on 2.4 GHz-band IEEE 802.15.4 standard. In this paper, the implementation results are compared to the results of OQPSK modulator and pulse-shaping block in terms of simulation waveform, design size, and synthesis run time. These blocks were designed using Verilog code through Xilinx ISE as a new design method and been implemented on Spartan3E XC3S500E field programmable gate array (FPGA). Current review shows that configurations for the implementation of OQPSK-pulse-shaping block, require 26.4% slices, 22.9% sliced flip-flops, and 15.5% look-up tables (LUTs), which is much better than the results of OQPSK modulator and pulse-shaping block. At clock frequencies of 2 MHz and 25 MHz, the synthesis run time for OQPSK-pulse-shaping block shows substantial improvement with 48 ns faster than the two blocks.