• DocumentCode
    3458806
  • Title

    Architectural Support for the Stream Execution Model on General-Purpose Processors

  • Author

    Gummaraju, Jayanth ; Erez, Mattan ; Coburn, Joel ; Rosenblum, Mendel ; Dally, William J.

  • Author_Institution
    Stanford Univ., Stanford
  • fYear
    2007
  • fDate
    15-19 Sept. 2007
  • Firstpage
    3
  • Lastpage
    12
  • Abstract
    There has recently been much interest in stream processing, both in industry (e.g., Cell, NVIDIA G80, ATI R580) and academia (e.g., Stanford Merrimac, MIT RAW), with stream programs becoming increasingly popular for both media and more general-purpose computing. Although a special style of programming called stream programming is needed to target these stream architectures, huge performance benefits can be achieved. In this paper, we minimally add architectural features to commodity general-purpose processors (e.g., Intel/AMD) to efficiently support the stream execution model. We design the extensions to reuse existing components of the general-purpose processor hardware as much as possible by investigating low-cost modifications to the CPU caches, hardware prefetcher, and the execution core. With a less than 1% increase in die area along with judicious use of a software runtime system, we can efficiently support stream programming on traditional processor cores. We evaluate our techniques by running scientific applications on a cycle-level simulation system. The results show that our system executes stream programs as efficiently as possible, limited only by the ALU performance and the memory bandwidth needed to feed the ALUs.
  • Keywords
    computer architecture; microcomputers; microprocessor chips; ALU performance; CPU cache modification; arithmetic logic unit; central processing unit; commodity general-purpose processor hardware; component reuse; cycle-level simulation system; execution core; hardware prefetcher; memory bandwidth; processor core; software runtime system; stream execution model; stream programming; Bandwidth; Computer architecture; Computer industry; Engines; Feeds; Hardware; Laser sintering; Memory management; Multicore processing; Prefetching;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Architecture and Compilation Techniques, 2007. PACT 2007. 16th International Conference on
  • Conference_Location
    Brasov
  • ISSN
    1089-795X
  • Print_ISBN
    978-0-7695-2944-8
  • Type

    conf

  • DOI
    10.1109/PACT.2007.4336195
  • Filename
    4336195