Novel circuits for radiation hardened memories

Author

Haraszti, T.P. ; Mento, R.P. ; Moyer, N.E. ; Grant, W.M.

fYear

1991

fDate

2-9 Nov. 1991

Firstpage

740

Abstract

Novel circuits, including orthogonal-shuffle-type write-read arrays, error correction by weighted bidirectional codes, and associative iterative repair circuits, are proposed for significant improvements of static random-access memory (SRAM) immunity against the effects of total dose and cosmic particle impacts. The implementation of the proposed circuit resulted in fault-tolerant 40-Mb and 10-Mb monolithic memories featuring a data rate of 120 MHz and power dissipation of 880 mW. These experimental serial-parallel memories were fabricated with a nonhardened standard CMOS processing technology, yet provided a total dose hardness of 1 Mrd and a projected SEU rate of 1*10/sup 12/ error/b/day. Using radiation-hardened processing, improvements by factors of 10 to 100 are predicted in both total dose hardness and SEU rate.<>

Keywords

CMOS integrated circuits; SRAM chips; nuclear electronics; radiation hardening (electronics); 120 MHz; 880 mW; SRAM; associative iterative repair circuits; cosmic particle impacts; error correction; fault-tolerant; monolithic memories; nonhardened standard CMOS processing technology; orthogonal-shuffle-type write-read arrays; power dissipation; projected SEU rate; radiation hardened memories; radiation-hardened processing; serial-parallel memories; static random-access memory; total dose; total dose hardness; weighted bidirectional codes; Aircraft; CMOS process; CMOS technology; Circuits; Degradation; Fault tolerance; Fault tolerant systems; Logic; Power dissipation; Radiation hardening;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium and Medical Imaging Conference, 1991., Conference Record of the 1991 IEEE

Conference_Location

Santa Fe, NM, USA

Print_ISBN

0-7803-0513-2

Type

conf

DOI

10.1109/NSSMIC.1991.259039

Filename

259039