DocumentCode
3458996
Title
An active suppression circuit for the reduction of di/dt event supply voltage variation
Author
Budnik, Mateusz ; Wood, Jo ; Roy, Kaushik
Author_Institution
Dept. of ECE, Valparaiso Univ., Valparaiso, IN
fYear
2008
fDate
24-28 Feb. 2008
Firstpage
893
Lastpage
896
Abstract
We demonstrate an integrated supply voltage variation suppression circuit for the reduction of di/dt event noise. The circuit was implemented in an 130 nm CMOS technology. For nominal conditions, the suppression circuit reduced the first droop supply voltage variation by 68.9%. The suppression circuit uses a digital control system which achieves a minimum response time of 1 ns.
Keywords
CMOS integrated circuits; active networks; CMOS technology; active suppression circuit; digital control system; event supply voltage variation; integrated supply voltage variation suppression circuit; supply voltage variation; CMOS technology; Capacitors; Delay; Digital control; RLC circuits; Regulators; Resonance; Resonant frequency; Sockets; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Applied Power Electronics Conference and Exposition, 2008. APEC 2008. Twenty-Third Annual IEEE
Conference_Location
Austin, TX
ISSN
1048-2334
Print_ISBN
978-1-4244-1873-2
Electronic_ISBN
1048-2334
Type
conf
DOI
10.1109/APEC.2008.4522826
Filename
4522826
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