Superconducting Super Collider data compression and driver/modulator architecture

Author

Cooke, B.J. ; Lackner, K.S. ; Sharp, D.H. ; Winter, C.L. ; Ziock, H.

Author_Institution

Los Alamos Nat. Lab., NM, USA

fYear

1991

fDate

2-9 Nov. 1991

Firstpage

799

Abstract

Presents a prototype architecture that provides chip-level data compression and high-speed optical drive capabilities for rad-hard Super Collider data acquisition applications. The data compression is accomplished through a pipelined edge-detection and clustering algorithm, while the driver/modulator uses high-throughput data-management techniques, including variable register lengths, bus queuing, and time-division-multiplexing for fast optical-data transmission. An architecture of this sort can provide efficient transmission of a very large number of events. A practical 4*128 compressor architecture is introduced to illustrate the algorithm.<>

Keywords

computer architecture; data acquisition; data compression; edge detection; optical links; physics computing; pipeline processing; synchrotrons; time division multiplexing; SSC; Superconducting Super Collider data compression; bus queuing; chip-level data compression; clustering algorithm; compressor architecture; driver/modulator architecture; fast optical-data transmission; high-speed optical drive capabilities; high-throughput data-management; pipelined edge-detection; prototype architecture; rad-hard Super Collider data acquisition; time-division-multiplexing; variable register lengths; Clustering algorithms; Data acquisition; Data compression; Detectors; Encoding; High speed optical techniques; Optical modulation; Pipelines; Radiation hardening; Strips;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium and Medical Imaging Conference, 1991., Conference Record of the 1991 IEEE

Conference_Location

Santa Fe, NM, USA

Print_ISBN

0-7803-0513-2

Type

conf

DOI

10.1109/NSSMIC.1991.259051

Filename

259051