DocumentCode :
3459418
Title :
Dual Boost High performances Power Factor Correction (PFC)
Author :
Attaianese, C. ; Nardi, V. ; Parillo, F. ; Tomasso, G.
Author_Institution :
Dept. of Autom., Univ. of Cassino, Cassino
fYear :
2008
fDate :
24-28 Feb. 2008
Firstpage :
1027
Lastpage :
1032
Abstract :
In this paper a novel power factor correction (PFC) dual boost scheme is proposed. It is based on an optimized power sharing where the active filtering approach is used to increase the current quality and at the same time to reduce the switching losses. A prototype of dual boost PFC controlled by a FPGA evaluation board was set up to implement the proposed control strategy. Both the simulation and experimental results show that the proposed strategy for PFC achieves near unity power factor and a not negligible switching losses reduction.
Keywords :
active filters; power factor correction; power filters; FPGA; PFC; active filtering approach; dual boost scheme; power factor correction; switching losses; Active filters; Circuits; Field programmable gate arrays; Filtering; Power factor correction; Prototypes; Reactive power; Switches; Switching frequency; Switching loss;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Applied Power Electronics Conference and Exposition, 2008. APEC 2008. Twenty-Third Annual IEEE
Conference_Location :
Austin, TX
ISSN :
1048-2334
Print_ISBN :
978-1-4244-1873-2
Electronic_ISBN :
1048-2334
Type :
conf
DOI :
10.1109/APEC.2008.4522848
Filename :
4522848
Link To Document :
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