A Speed-Improved Architecture for CMOS Programmable Divider

Author

Hsu, Ching-Wen ; Lin, Yu-Sheng ; Lu, Chun-Lin ; Wang, Yeong-Her ; Cheng, Kuo-Sheng

Author_Institution

Dept. of Comput. & Commun., Kun Shan Univ., Taiwan

fYear

2009

fDate

7-9 Dec. 2009

Firstpage

585

Lastpage

588

Abstract

This paper proposes a novel dynamic logic which not only has a lower output parasitic capacitance but also has a switchable characteristic to achieve the speed improvement in the application of programmable divider. The speed of some logic circuits is discussed in this paper. A 16-GHz divide-by-two frequency divider based on the proposed dynamic logic has been demonstrated in TSMC 0.13-mum CMOS process, too. After a successful simulation, the implemented frequency divider has an operating range from 10.5 to 16.5 GHz and a maximum input sensitivity of 5 mV in amplitude at 13.5 GHz under a supply voltage of 1.3 V and a core power consumption of 4.7 mW.

Keywords

CMOS logic circuits; frequency dividers; microwave circuits; CMOS programmable divider; TSMC CMOS process; divide-by-two frequency divider; dynamic logic; frequency 10.5 GHz to 16.5 GHz; logic circuit speed; lower-output parasitic capacitance; power 4.7 mW; size 0.13 mum; speed improvement; speed-improved architecture; voltage 1.3 V; CMOS logic circuits; CMOS process; Circuit simulation; Frequency conversion; Inverters; Logic circuits; MOS devices; Parasitic capacitance; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Innovative Computing, Information and Control (ICICIC), 2009 Fourth International Conference on

Conference_Location

Kaohsiung

Print_ISBN

978-1-4244-5543-0

Type

conf

DOI

10.1109/ICICIC.2009.54

Filename

5412507