• DocumentCode
    3460137
  • Title

    Characterization of bitline stress effects on flash cell after program/erase cycle

  • Author

    Liu, Y.C. ; Guo, J.C. ; Chang, K.L. ; Huang, C.I. ; Wang, M.T. ; Chang, A. ; Shone, F.

  • Author_Institution
    Device Dept., Macronix Int. Co. Ltd., Taiwan, China
  • fYear
    1997
  • fDate
    8-10 Apr 1997
  • Firstpage
    97
  • Lastpage
    103
  • Abstract
    The impact of degradation of Flash memory cell characteristics caused by bitline stress during program/erase cycling is investigated considering the accentuated generation rate of negative oxide trap charges and interface-states. A special emphasis is focused on the observation of a significant amount of hole traps and their movement into the channel region. These oxide damages dramatically alter the device characteristics, and initiate severe read-disturb issue
  • Keywords
    EPROM; hole traps; integrated memory circuits; interface states; bitline stress; degradation; flash memory cell; hole traps; interface states; negative oxide trapped charge; program/erase cycling; read-disturb; Channel hot electron injection; Degradation; EPROM; Flash memory cells; Hot carriers; Nonvolatile memory; Stress; Testing; Threshold voltage; Tunneling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 1997. 35th Annual Proceedings., IEEE International
  • Conference_Location
    Denver, CO
  • Print_ISBN
    0-7803-3575-9
  • Type

    conf

  • DOI
    10.1109/RELPHY.1997.584244
  • Filename
    584244
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3460137