DocumentCode :
3460176
Title :
Events and constraints: a graphical editor for capturing logic requirements of programs
Author :
Smith, Margaret H. ; Holzmann, Gerard J. ; Etessami, Kousha
Author_Institution :
Lucent Technol. Bell Labs., Murray Hill, NJ, USA
fYear :
2001
fDate :
2001
Firstpage :
14
Lastpage :
22
Abstract :
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model-checking tools expect the user to supply a formal statement of the correctness requirements to be checked in temporal logic. Expressing non-trivial requirements in logic, however, can be challenging. To address this problem, we developed a graphical tool, called the TimeLine Editor, that simplifies the formalization of certain kinds of requirements. A series of events and required system responses are placed on a timeline. The user converts the timeline specification automatically into a test automaton that can be used directly by a logic model checker or for traditional test-sequence generation. We have used the TimeLine Editor to verify the call processing code for Lucent´s PathStar access server against the TelCordia LSSGR [LATA (local access and transport area) Switching Systems Generic Requirements] standards. The TimeLine Editor simplified the task of converting a large body of English prose requirements into formal, yet readable, logic requirements
Keywords :
computer aided software engineering; formal specification; graphical user interfaces; program debugging; program testing; program verification; sequences; software standards; telecommunication computing; telecommunication switching; temporal logic; visual programming; English prose requirements; LATA Switching Systems Generic Requirements; Lucent PathStar access server; TelCordia LSSGR standards; TimeLine Editor; call processing code verification; constraints; events; formal correctness requirements; graphical editing tool; local access and transport area; logic model checker; nontrivial requirements; program logic requirements capture; readable logic requirements; required system responses; requirements formalization; software application debugging; software testing; software verification; temporal logic; test automaton; test sequence generation; timeline specification; Application software; Automata; Automatic testing; Computer bugs; Logic testing; Software debugging; Software testing; Software tools; Switches; Telephony;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Requirements Engineering, 2001. Proceedings. Fifth IEEE International Symposium on
Conference_Location :
Toronto, Ont.
Print_ISBN :
0-7695-1125-2
Type :
conf
DOI :
10.1109/ISRE.2001.948539
Filename :
948539
Link To Document :
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