• DocumentCode
    3460210
  • Title

    Flip chip underfill reliability of CSP during IR reflow soldering

  • Author

    Ohshima, Yumiko ; Nakazawa, Takahito ; Doi, Kazuhide ; Aoki, Hideo ; Hiruta, Yoichi

  • Author_Institution
    Adv. Packaging Dev. Sect., Toshiba Corp., Yokohama, Japan
  • fYear
    1997
  • fDate
    8-10 Apr 1997
  • Firstpage
    124
  • Lastpage
    128
  • Abstract
    Reliability of flip chip CSP (Chip Scale Package) was investigated. The underfill resin for CSP has high saturation content of moisture absorption, compared to a conventional mold resin. The IR reflow test showed no delamination at the underfill interfaces and no package cracking in a flip chip CSP with a ceramic substrate and voidless underfill under the JEDEC LEVEL 1 and 2 conditions. However, it was found out that delamination and package cracking occurred in the IR reflow test under the JEDEC LEVEL 1 when the flip chip CSP has voids in the underfill. The underfill reliability results by IR reflow test confirmed superior reliability of the flip chip CSP with a ceramic substrate and void controlled underfill
  • Keywords
    flip-chip devices; integrated circuit packaging; integrated circuit reliability; reflow soldering; IR reflow soldering; JEDEC LEVEL 1; JEDEC LEVEL 2; ceramic substrate; chip scale package; cracking; flip chip CSP; interface delamination; moisture absorption; reliability; underfill resin; voids; Ceramics; Chip scale packaging; Delamination; Flip chip; Moisture; Reflow soldering; Resins; Semiconductor device packaging; Testing; Viscosity;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 1997. 35th Annual Proceedings., IEEE International
  • Conference_Location
    Denver, CO
  • Print_ISBN
    0-7803-3575-9
  • Type

    conf

  • DOI
    10.1109/RELPHY.1997.584248
  • Filename
    584248