Title :
60 GHz cascode LNA with interstage matching: performance comparison between 130nm BiCMOS and 65nm CMOS-SOI technologies
Author :
Majek, C. ; Severino, R.R. ; Taris, T. ; Deval, Y. ; Mariano, A. ; Bégueret, J-B ; Belot, D.
Author_Institution :
IMS Lab., Univ. of Bordeaux, Bordeaux, France
Abstract :
This paper presents a comparative study between two mm-wave technologies from STMicroelectronics: 130 nm BiCMOS and 65 nm CMOS-SOI, through the implementation of a single stage LNA at 60 GHz. Both distributed and lumped design approaches are investigated to work out the best trade-off between silicon saving and performances. The two circuits achieve respectively 12 dB and 6 dB gain, 3.6 dB and 4.5 dB noise figure under 2.5V and 1.2V supply voltage for BiCMOS9MW and CMOS-SOI technologies. The LNA are based on cascode topology with a specific interstage matching for ft and fmax improvement. The current density and transistor sizing are set to perform the lowest NF at 60 GHz, the current consumption is 3.7 mA and 13 mA for BiCMOS9MW and CMOS-SOI LNA respectively.
Keywords :
BiCMOS integrated circuits; CMOS integrated circuits; MIMIC; integrated circuit design; low noise amplifiers; silicon-on-insulator; BiCMOS technology; CMOS-SOI technology; cascode LNA; current 13 mA; current 3.7 mA; distributed design; frequency 60 GHz; gain 12 dB; gain 6 dB; interstage matching; lumped design; millimeter wave technology; noise figure 3.6 dB; noise figure 4.5 dB; silicon saving; size 130 nm; size 65 nm; voltage 1.2 V; voltage 2.5 V; BiCMOS integrated circuits; CMOS technology; Circuits and systems; Current density; Frequency; Noise measurement; Q factor; Silicon; Space technology; Topology; BiCMOS; CMOS-SOI; LNA; interstage matching; mm-waves;
Conference_Titel :
Signals, Circuits and Systems (SCS), 2009 3rd International Conference on
Conference_Location :
Medenine
Print_ISBN :
978-1-4244-4397-0
Electronic_ISBN :
978-1-4244-4398-7
DOI :
10.1109/ICSCS.2009.5412569
