Title :
Failure rate model for thin film cracking in plastic ICs
Author :
Blish, R.C., II ; Vaney, P.R.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
Thin film cracking (TFC) failure rate in temperature cycling was modeled over a wide range of temperature swings as a function of delta T/sup m/. The value of m is approximately 12 for TFC. Failure analysis showed the root cause of the failures to be wide top metal bus metallization lines. Accordingly one element of proper design has been to use top metal lines that appear as lattice-work rather than planks. Finite element analysis efforts lend credence to the design strategy, slotted top metal lines. The substitution of this lattice-work layout for the solid line produces a twofold improvement in applied load, while the structural stability of each individual line segment is also greater than the original single, unslotted line. Thus, the loads upon and the stresses transmitted by top metal lines are reduced significantly. Examples are shown to illustrate how effective this design strategy for building in reliability has been, reducing failure rate for a given environmental stress by 1000-fold.<>
Keywords :
failure analysis; integrated circuit testing; metallisation; packaging; environmental stress; failure rate; finite element analysis; lattice-work; model; plastic ICs; structural stability; temperature cycling; thin film cracking; wide top metal bus metallization lines; Buildings; Electric shock; Failure analysis; Fatigue; Finite element methods; Gold; Intermetallic; Plastic films; Temperature distribution; Thermal stresses;
Conference_Titel :
Reliability Physics Symposium, 1991, 29th Annual Proceedings., International
Conference_Location :
Las Vegas, NV, USA
Print_ISBN :
0-87942-680-2
DOI :
10.1109/RELPHY.1991.145982