DocumentCode
3460807
Title
Study of a CMOS I/O protection circuit using circuit-level simulation
Author
Li, T. ; Suh, D. ; Ramaswamy, S. ; Bendix, P. ; Rosenbaum, E. ; Kapoor, A. ; Kang, S.M.
Author_Institution
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
fYear
1997
fDate
8-10 Apr 1997
Firstpage
333
Lastpage
338
Abstract
In this work, circuit-level simulation is conducted for a typical two-stage protection circuit. We demonstrate that the circuit failure mechanism is correctly predicted by simulation. Furthermore, the current protection levels estimated by simulation are in good agreement with the experiments; therefore, circuit-level simulation can be used to predict the HBM-ESD protection level. In addition, the failure site is explained by simulation
Keywords
CMOS integrated circuits; circuit analysis computing; electrostatic discharge; failure analysis; integrated circuit measurement; integrated circuit reliability; protection; CMOS I/O protection circuit; HBM-ESD protection level; circuit failure mechanism; circuit-level simulation; failure site; transmission line pulsing technique; two-stage protection circuit; visual failure analysis; Circuit simulation; Electrostatic discharge; Fingers; Leg; MOS devices; MOSFETs; Predictive models; Protection; Resistors; Thyristors;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 1997. 35th Annual Proceedings., IEEE International
Conference_Location
Denver, CO
Print_ISBN
0-7803-3575-9
Type
conf
DOI
10.1109/RELPHY.1997.584283
Filename
584283
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