DocumentCode
346084
Title
A new systematic yield ramp methodology
Author
Nemoto, Kae ; Walanabe, K. ; Ono, M. ; Ikeda, Yoko ; Saiki, Koji
Author_Institution
Production Eng. Res. Lab., Hitachi Ltd., Yokohama, Japan
fYear
1999
fDate
1999
Firstpage
21
Lastpage
24
Abstract
This paper presents a systematic yield ramp methodology that is based on defect reduction. The proposed approach uses statistical regression analysis to find the origin of the defects associated with yield loss. Moreover, in order to verify its usefulness, the proposed methodology is applied to high volume memory device production resulting in yield improvement due to shortening the time required for defect elimination
Keywords
integrated circuit yield; quality control; statistical analysis; IC manufacture; defect elimination; defect reduction; high volume production; memory device production; statistical regression analysis; systematic yield ramp methodology; yield improvement; yield loss; Electrons; Inspection; Laboratories; Manufacturing processes; Performance analysis; Product design; Production; Profitability; Random access memory; Regression analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI
Conference_Location
Boston, MA
ISSN
1078-8743
Print_ISBN
0-7803-5217-3
Type
conf
DOI
10.1109/ASMC.1999.798174
Filename
798174
Link To Document