DocumentCode :
3460866
Title :
Power and delay comparison of binary and quaternary arithmetic circuits
Author :
Lazzari, Cristiano ; Flores, Paulo ; Monteiro, Jose Carlos
Author_Institution :
ALGOS Group, INESC-ID, Lisbon, Portugal
fYear :
2009
fDate :
6-8 Nov. 2009
Firstpage :
1
Lastpage :
6
Abstract :
Interconnections play a crucial role in todays deep sub-micron designs because they dominate the delay, power and area. This is especially critical for modern million-gates FPGAs, where as much as 90% of chip area is devoted to interconnections. Multiple-valued logic allows for the reduction of the required number of signals in the circuit, hence can serve as a means to effectively curtail the impact of interconnections. We present in this paper a comparison of binary and quaternary implementations of arithmetic modules based on lookup table structures using a voltage-mode circuits. Our assessment demonstrates that significant a power reduction is possible through the use of quaternary structures, with very low delay penalties.
Keywords :
adders; multivalued logic circuits; table lookup; binary circuits; lookup table structures; multiple-valued logic; power consumption; quaternary arithmetic circuits; voltage-mode circuits; Adders; Arithmetic; Delay; Energy consumption; Field programmable gate arrays; Integrated circuit interconnections; Logic circuits; Power system interconnection; Table lookup; Voltage; Arithmetic Circuits; Delay and Power Consumption; FPGA Synthesis; Quaternary Logic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Circuits and Systems (SCS), 2009 3rd International Conference on
Conference_Location :
Medenine
Print_ISBN :
978-1-4244-4397-0
Electronic_ISBN :
978-1-4244-4398-7
Type :
conf
DOI :
10.1109/ICSCS.2009.5412586
Filename :
5412586
Link To Document :
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