High memory throughput FPGA architecture for high-definition Belief-Propagation stereo matching

3D systems are starting to be included in real applications. One of the most commonly used groups of 3D algorithms is the stereo matching one. It obtains a stereoscopic image, which includes information about the distance from the camera to the objects in the image. Several algorithms have been proposed to obtain an accurate depth map. Among them, those based on Belief-Propagation message passing have shown great performance. However, the iterative process carried out leads to high consumption of resources, especially memory traffic. Implementations in CPUs are very slow. Moreover, the inherent parallelism this algorithm shows makes it a good candidate either for GPU or FPGA implementations. In this paper we present a high-definition depth estimation architecture based on BP for FPGA platforms. The architecture proposed uses a bank of DDR2 memories able to work at 200 MHz to reduce the execution time required for obtaining high-definition depth maps. Moreover, to generate data at the maximum frequency allowed by the DDR2 memory, several improvements in the architecture are proposed. The architecture has been implemented in a Xilinx Virtex 5 330 VLX FPGA. As a result, a high-definition depth map with 96 disparity levels can be obtained in less than 0.4 seconds.