A novel PLL design method applied to grid fault condition

Author

Xueguang, Zhang ; Dianguo, Xu ; Weiwei, Li

Author_Institution

Harbin Inst. of Technol., Harbin

fYear

2008

fDate

24-28 Feb. 2008

Firstpage

2016

Lastpage

2020

Abstract

A novel three phase PLL (phase lock loop) design method was proposed based on variable period sampling delayed signal cancellation (DSC) method. This PLL can be used in grid fault condition. The influence caused by unbalanced grid voltage will be eliminated effectively through delayed signal cancellation. Variable period sampling was used to trace the frequency deviation and eliminate phase shift offset which is caused by frequency deviation. The amplitude, phase and frequency of both the positive and negative sequence voltage will be detected in double synchronous reference frame. The proposed method was verified by experiment results.

Keywords

fault diagnosis; phase locked loops; power grids; wind power plants; PLL design method; delayed signal cancellation method; double synchronous reference frame; frequency deviation; grid fault condition; phase lock loop; phase shift offset elimination; variable period sampling; Band pass filters; Design methodology; Fluctuations; Frequency; Low pass filters; Mesh generation; Phase locked loops; Sampling methods; Voltage; Wind energy generation; DSC; PLL; double synchronous reference frame; variable period sampling; wind generation system;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Power Electronics Conference and Exposition, 2008. APEC 2008. Twenty-Third Annual IEEE

Conference_Location

Austin, TX

ISSN

1048-2334

Print_ISBN

978-1-4244-1873-2

Electronic_ISBN

1048-2334

Type

conf

DOI

10.1109/APEC.2008.4523004

Filename

4523004