Abstract :
The scaling of CMOS transistors is discussed from the perspective of the 2005 International Technology Roadmap for Semiconductors. Numerous critical scaling challenges are identified, including excessive gate leakage current, difficulty in controlling short-channel effects, need for enhanced mobility, and others. To deal with these, numerous major technological innovations will be required, such as high-k gate dielectric, strained silicon for enhanced mobility, and non-classical devices (e.g., FinFETs)
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit design; leakage currents; 2005 International Technology Roadmap for Semiconductors; CMOS transistors; enhanced mobility; gate CMOSFET scaling; gate leakage current; short-channel effects; CMOSFETs; Capacitance; Clocks; Delay; Leakage current; Logic; MOSFET circuits; Power MOSFET; Power dissipation; Power supplies;
