FPGA-based fine grain processor array design considerations

Author

Erenyi, I. ; Vassányi, István

Author_Institution

KFKI Res. Inst. for Meas. & Comput. Techniques, Budapest, Hungary

Volume

2

fYear

1996

fDate

13-16 Oct 1996

Firstpage

659

Abstract

Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper gives geometric criteria for an optimal “jigsaw tessellated” processor cell, and cost function for cell placement. The paper demonstrates the use of FPGA-based processor arrays by the implementation results of cellular image processing algorithms. The outlined concepts are being implemented in a placement-routing tool

Keywords

field programmable gate arrays; image processing; network routing; parallel architectures; reconfigurable architectures; FPGA-based fine grain processor array; cell placement; cellular image processing algorithms; cost function; geometric criteria; massively parallel array architectures; optimal jigsaw tessellated processor cell; placement-routing tool; processor array design; Algorithm design and analysis; Cost function; Field programmable gate arrays; Hardware; Process design; Programmable logic arrays; Routing; Systolic arrays; Tiles; Transforms;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on

Conference_Location

Rodos

Print_ISBN

0-7803-3650-X

Type

conf

DOI

10.1109/ICECS.1996.584448

Filename

584448