Title :
Challenges for sub-10 nm CMOS devices
Author_Institution :
Selete, Inc., Ibaraki
Abstract :
Sub-10nm CMOS devices are the critical issue, because CMOS scaling is going to be sub-25nm regime. Scaling issues of nano-size MOSFETs can be discussed on the basis of sub-10 nm MOSFETs characteristics, which have been developed and confirmed switching characteristics and low-temperature characteristics. Studying device limitation issues and developing new breakthrough technologies are required to challenge sub-10-nm CMOS devices
Keywords :
CMOS integrated circuits; MOSFET; nanotechnology; 10 nm; 25 nm; CMOS devices; CMOS scaling; device limitation; nanosize MOSFET; CMOS technology; Kelvin; Low voltage; MOSFETs; Microelectronics; Silicon; Temperature dependence; Transconductance; Tunneling; Voltage control;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306046
