Title :
CMOS devices architectures for the end of the roadmap and beyond
Author :
Deleonibus, S. ; De Salvo, B. ; Clavelier, L. ; Ernst, T. ; Faynot, O. ; Poiroux, T. ; Vinet, M.
Author_Institution :
CEA-LETI/NANOTEC, Grenoble
Abstract :
Since the end of the last millenium, the microelectronics industry is facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS devices structure or if new devices architectures are implemented. The demand for low voltage, low power and high performance are the great challenges for the engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. Multigate architectures allow to increase devices drivability, reduce power, new memory devices opportunities and will be necessary to develop future applications. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. By introducing new materials (HiK, Ge, diamond/graphite Carbon,...), Si based CMOS will be scaled beyond the ITRS as the system-on-chip platform
Keywords :
CMOS integrated circuits; MOSFET; integrated circuits; low-power electronics; 5 nm; 50 nm; CMOS devices architectures; CMOS devices scaling; ITRS; gate dielectric; linear scaling; low supply voltage management; memory devices; metal gate; microelectronics industry; multigate architectures; power consumption; system-on-chip platform; Diamond-like carbon; Dielectric materials; Energy consumption; Energy management; Low voltage; Microelectronics; Organic materials; Power engineering and energy; Power system management; System-on-a-chip;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306074
