Manufacturing considerations of lithography independent nano-MOS-transisters in the sub-25 nm-region

The 2005 International Technology Roadmap for Semiconductors predicts a printed minimum MOS-transistor channel length of 9 nm for the year 2020, which results in a physical gate length of only 6 nm. The resolution of optical lithography still dramatically increases, but known and proved solutions for structure sizes significantly below 50 nm do not exist until now. Above these dimensions the known solutions are only affordable to a very diminutive group of manufactures due to the extraordinary mask costs. Therefore this paper presents and compares different methods of fabrication of MOS-transistors with a channel area smaller than W = 25 nm and L = 25 nm with low demands to the used lithography. They are all based on our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, while the channel width was not scaled and stayed at the dimensions of the optical lithography (e.g. 0,8 mum). The used techniques are easily transferable to almost any other technology line and result in an excellent homogeneity and reproducibility of the generated structure size. By this means it is possible to examine the future nano-MOS-transistors regarding their electrical characteristics including low temperature measurements and statistical measurements at very low costs