Characterization of the self-aligned pseudo-SOI device structures

We are trying to submit with this paper a new concept concerning the partial silicon-on-insulator (SOI) process, aiming to fabricate the self-aligned pseudo-SOI device structures - (a) the silicon on partial insulator with block oxide FET (bSPIFET), and (b) the partially insulating oxide (PiOX) under source/drain (S/D) (PUSD) partially insulated field-effect transistor (PUSD PiFET) (Yeo et al., 2004) respectively. Our proposed concept - pseudo-SOI MOSFETs - would attain the high-performance via its block oxide utilized to block the electric field lines from the drain to the body of the devices, and eliminate both the floating-body effects (FBEs) and the self-heating effects (SHEs) caused by its body-tied schemes utilized to dissipate the hole/heat being generated from the channel region of the devices. In addition, we wish to apply the self-aligned technique to fabricate the proposed pseudo-SOI devices, seeking to improve in effect the misalignment problem in using the ULSI application