DocumentCode :
3462546
Title :
A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor
Author :
Tremblay, Marc ; Chaudhry, Shailender
Author_Institution :
Sun Microsyst., Santa Clara, CA
fYear :
2008
fDate :
3-7 Feb. 2008
Firstpage :
82
Lastpage :
83
Abstract :
The goals for this high-end commercial microprocessor are high throughput and high single-thread performance, mainframe-class reliability, hardware transactional memory, and linear scalability. We show how these goals are met by the logical and physical design of this 2.3GHz 396mm2 16-core 32-thread plus 32-scout-thread microprocessor.
Keywords :
microprocessor chips; multi-threading; 16-core 32-thread 32-scout-thread SPARC processor; chip multithreading; frequency 2.3 GHz; hardware transactional memory; linear scalability; mainframe-class reliability; microprocessor; single-thread performance; size 65 nm; Bandwidth; Delay; Microprocessors; Out of order; Pipelines; Protection; Registers; Switches; Throughput; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
Type :
conf
DOI :
10.1109/ISSCC.2008.4523067
Filename :
4523067
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3462546
بازگشت