Title :
An 8Gb/s Transceiver with 3Ã\x97-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane
Author :
Fukuda, K. ; Yamashita, H. ; Yuki, F. ; Yagyu, M. ; Nemoto, R. ; Takemoto, T. ; Saito, T. ; Chujo, N. ; Yamamoto, K. ; Kanai, H. ; Hayashi, A.
Author_Institution :
Hitachi, Tokyo
Abstract :
IT systems such as servers and routers need high-speed lower- power area-efficient chip-to-chip interconnections through backplane boards. These interconnections must overcome signal degradation due to the large insertion loss of low-cost boards. In this work, a 90nm CMOS 8Gb/s transceiver is developed. A TX 5- tap FFE, an RX analog equalizer, and a 2-tap DFE combined with a 2-threshold eye-tracking CDR achieve a BER of less than 10-12 through a 160cm backplane board with -36.8dB loss at 4GHz and a transceiver power consumption of 232mW (transmission efficiency of 1.2Gb/sxdB/mW).
Keywords :
CMOS integrated circuits; equalisers; error statistics; integrated circuit interconnections; synchronisation; transceivers; BER; CDR circuit; CMOS transceiver; analog equalizer; backplane boards; bit rate 8 Gbit/s; chip-to-chip interconnections; clock and data recovery; frequency 4 GHz; loss -36.8 dB; power 232 mW; size 90 nm; threshold eye-tracking; Backplanes; Bit error rate; Decision feedback equalizers; Degradation; Energy consumption; Insertion loss; Integrated circuit interconnections; Power system interconnection; Propagation losses; Transceivers;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523075
