Title :
Process induced stress for CMOS performance improvement
Author :
Fang, S. ; Tan, S.S. ; Dyer, T. ; Luo, Z. ; Yan, J. ; Kim, J.J. ; Rovedo, N. ; Lun, Z. ; Yuan, J. ; Chen, X. ; Chan, V. ; Tang, T.J. ; Amos, R. ; Ng, H. ; Ieong, M. ; Iyer, S. ; Crowder, S.
Author_Institution :
Semicond. Res. & Dev. Center, IBM, Hopewell Junction, NY
Abstract :
The integration of 3 major techniques of process induced stress, stress memory technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT), has been demonstrate for advanced CMOS technology. The device performance improvement from each technique and their addability are discussed
Keywords :
CMOS integrated circuits; semiconductor technology; CMOS performance improvement; dual stress liners; process induced stress; stress memory technique; stress proximity technique; CMOS process; CMOS technology; Capacitive sensors; Compressive stress; Costs; DSL; Electron mobility; MOSFET circuits; Surface-mount technology; Tensile stress;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306090
