The impact of stress enhanced technology for sub-90nm SOI MOSFETs

For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length of diffusion (LOD) to control the tensile and compressive stress in channel regions were developed. In this work, in order to investigate the interactive stress effects of GC layer film thickness, LOD and gate width on device´s characteristic and hot-carrier reliability; devices with various GC layer (1100A, 700A, SiN380), LOD (0.45mum ~4.5mum) and width (0.18mum~10mum) were fabricated. It is found that devices with 700A GC layer layer (appropriate tensile stress), 4.5 mum LOD (low compressive stress) and 0.18mum gate width (narrow width) possess the better performance