Title :
A 20Gb/s Duobinary Transceiver in 90nm CMOS
Author :
Lee, Jri ; Chen, Ming-Shuan ; Wang, Huai-De
Author_Institution :
Nat. Taiwan Univ., Taipei
Abstract :
The ever growing volume of backplane communications pushes the data rate toward 20Gb/s for the next-generation transceivers. Over the years, chip designers have been seeking different data formats to overcome the loss of electrical channels. Among the existing solutions, duobinary signaling manifests itself in bandwidth efficiency as (1) its spectrum occupies only half as wide as that of NRZ data; (2) it incorporates the intrinsic roll-off bandwidth of the channel as part of the desired response. The design and experimental verification of a fully-integrated duobinary transceiver in 90nm CMOS is described. The transceiver achieves 20Gb/s error-free transmission over a 40cm Rogers and a 10cm FR4 channels.
Keywords :
CMOS integrated circuits; transceivers; CMOS; backplane communications; bandwidth efficiency; bit rate 20 Gbit/s; duobinary signaling; electrical channels; fully-integrated duobinary transceiver; next-generation transceivers; roll-off bandwidth; size 90 nm; Bandwidth; Circuits; Clocks; Jitter; Optical signal processing; Optical transmitters; Space vector pulse width modulation; Transceivers; Transfer functions; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523077
