Title :
Mobility enhancement technology
Author :
Yuan, F. ; Liu, C.W.
Author_Institution :
Dept. of Electr. Eng., National Taiwan Univ., Taipei
Abstract :
The appropriate external stress can enhance device and circuit performance. The 7.4% speed enhancement is achieved for the 250 nm node ring oscillator under uniaxial tensile strain for mutually perpendicular layout of the NFET and the PFET. The speed enhancement is less than 1.5% for the conventional parallel layout of the NFET and the PFET. The ultra thin strained Si0.2Ge0.8 quantum well channel (~5 nm) directly grown on Si substrate is also demonstrated. The SiGe quantum well channel using Pt Schottky barrier and SiO2 gate dielectrics reveals a ~3.2times current enhancement and ~3times mobility enhancement as compared to the bulk Si PFET. The compressive strain on SiGe quantum well can further enhance the hole mobility in Si 0.2Ge0.8 channel
Keywords :
CMOS integrated circuits; Schottky barriers; carrier mobility; integrated circuit layout; oscillators; quantum well devices; semiconductor technology; 250 nm; Schottky barrier; Si0.2Ge0.8; SiO2; circuit performance; device performance; external stress; hole mobility; mobility enhancement; ring oscillator; ultra thin strained quantum well channel; uniaxial tensile strain; 1f noise; Capacitive sensors; Circuit optimization; Costs; Dielectric substrates; Germanium silicon alloys; MOSFET circuits; Packaging; Silicon germanium; Tensile strain;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306092
