A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

Author

Chi, Hyung-Joon ; Lee, Jae-seung ; Jeon, Seong-Hwan ; Bae, Seung-Jun ; Sim, Jae-Yoon ; Park, Hong-June

Author_Institution

Pohang Univ. of Sci. & Technol., Pohang

fYear

2008

fDate

3-7 Feb. 2008

Firstpage

112

Lastpage

600

Abstract

A 3.2Gb/s single-ended current-integrating DFE receiver with 8b parallel data for 2-drop DRAM interface is implemented in a 0.18mum CMOS process. The reference voltage for the receiver is generated internally to reduce the external coupling noise. A single-loop implementation of sign-sign LMS algorithm is used to decide the single-tap equalization coefficient of the DFE receiver instead of the previous dual-loop implementation.

Keywords

DRAM chips; decision feedback equalisers; least mean squares methods; receivers; DFE receivers; DRAM interface; bit rate 3.2 Gbit/s; coupling noise reduction; decision feedback equalisers; internal reference voltage; least mean squares methods; single-tap equalization coefficient; size 0.18 mum; Calibration; Circuits; Decision feedback equalizers; Frequency; Phase locked loops; Random access memory; Semiconductor device measurement; Transceivers; Transmitters; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-2010-0

Electronic_ISBN

978-1-4244-2011-7

Type

conf

DOI

10.1109/ISSCC.2008.4523082

Filename

4523082