Clock distribution using multiple voltages

Author

Pangjun, Jatuchai ; Sapatnekar, Sachin S.

Author_Institution

Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA

fYear

1999

fDate

17-17 Aug. 1999

Firstpage

145

Lastpage

150

Abstract

Clock networks account for a significant fraction of the power dissipation of a chip and are critical to the performance. This paper presents theory and algorithms for building a low power clock tree. Two low power schemes are used: a reduced swing scheme and one using multiple supply voltages. We analyze the issue of tree construction and present conclusions relevant to various technology generations according to the National Technology Roadmap of Semiconductors (NTRS). Our experimental results show that the power could be saved an average of 45% for a 0.25 /spl mu/m technology using multiple supply voltages, and 31% using reduced swing buffers.

Keywords

buffer circuits; circuit layout CAD; clocks; integrated circuit layout; integrated logic circuits; logic design; low-power electronics; network routing; trees (mathematics); 0.25 mum; National Technology Roadmap of Semiconductors; clock distribution; clock networks; level converter circuits; low power clock tree; multiple supply voltages; multiple voltages; power dissipation; reduced swing buffers; reduced swing scheme; tree construction; Buildings; Capacitance; Clocks; Delay; Network synthesis; Network topology; Power dissipation; Routing; Voltage; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on

Conference_Location

San Diego, CA, USA

Print_ISBN

1-58113-133-X

Type

conf

Filename

799430