Title :
Monotonic static CMOS and dual V/sub T/ technology
Author :
Thorp, Tyler ; Yee, Gin ; Sechen, Carl
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Abstract :
We developed a methodology and tools for synthesizing monotonic static CMOS networks, which consist of alternating low-skewed and high-skewed static gates. When used with a dual V/sub T/ process, monotonic static CMOS can simultaneously reduce standby static power and increase performance by using low V/sub T/ devices in the evaluation networks and making all other devices high V/sub T/. Experimental results show monotonic static CMOS to be 1.67 times faster than traditional static CMOS.
Keywords :
CMOS logic circuits; combinational circuits; logic design; logic gates; low-power electronics; dual V/sub T/ process; dual threshold voltage technology; high-skewed static gates; low-skewed static gates; monotonic static CMOS; standby static power reduction; CMOS logic circuits; CMOS process; CMOS technology; Logic devices; Logic gates; Maintenance; Permission; Power dissipation; Switches; Threshold voltage;
Conference_Titel :
Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on
Conference_Location :
San Diego, CA, USA
Print_ISBN :
1-58113-133-X
