Title :
Effective suppression of fermi level pinning in poly-Si/HfO/sub 2/ gate stack by using poly-SiGe gate
Author :
Yu, Xiongfei ; Yu, Mingbin ; Zhu, Chunxiang
Author_Institution :
Dept. of Electr. & Comput. Eng., Singapore Nat. Univ.
Abstract :
In this work, it was demonstrated that the Fermi level pinning in poly-Si/HfO2 can be effectively suppressed by using poly-SiGe gate. Threshold voltage of -1.02 V in poly-Si/HfO2 PFET was tuned to -0.81 V in poly-Si/Al2O3/HfO2, and further reduced to -0.49 V in poly-Si/poly-SiGe/Al2O3/HfO2. At the same time, Vth of 0.3 V for NFET was achieved in this poly-SiGe gate stack. Moreover, Vth stability was remarkably improved by using poly-SiGe gate and Al2O3 capping layer. The improvements shown in this poly-SiGe gate stack could be due to the suppressed formation of oxygen vacancies
Keywords :
Fermi level; Ge-Si alloys; aluminium compounds; field effect transistors; hafnium compounds; silicon; -0.49 V; -0.81 V; -1.02 V; 0.3 V; Fermi level pinning suppression; PFET; Si-Al2O3-HfO2; Si-SiGe-Al2O3-HfO2; gate stack; threshold voltage stability; Aluminum oxide; Annealing; Buffer layers; Dielectrics; Germanium silicon alloys; Hafnium oxide; Microelectronics; Silicon germanium; Stability; Threshold voltage;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306123
