DocumentCode :
346290
Title :
Power scalable processing using distributed arithmetic
Author :
Amirtharajah, Rajeevan ; Xanthopoulos, Thucydides ; Chandrakasan, Anantha
Author_Institution :
MIT, Cambridge, MA, USA
fYear :
1999
fDate :
17-17 Aug. 1999
Firstpage :
170
Lastpage :
175
Abstract :
A recent trend in low power design has been the employment of reduced precision processing methods for decreasing arithmetic activity and average power dissipation. Such designs can trade off power and arithmetic precision as system requirements change. This work explores the potential of Distributed Arithmetic (DA) computation structures for low power precision-on-demand computation. We present two proof-of-concept VLSI implementations whose power dissipation changes according to the precision of the computation performed.
Keywords :
VLSI; digital signal processing chips; discrete cosine transforms; distributed arithmetic; low-power electronics; DCT core processor; VLSI implementations; arithmetic activity reduction; arithmetic precision; average power dissipation reduction; distributed arithmetic computation structures; low power DSP; low power design; low power precision-on-demand computation; power scalable processing; reduced precision processing methods; Arithmetic; Collaborative work; Concurrent computing; Distributed computing; Filtering; Finite impulse response filter; Frequency estimation; Power dissipation; Speech; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on
Conference_Location :
San Diego, CA, USA
Print_ISBN :
1-58113-133-X
Type :
conf
Filename :
799434
Link To Document :
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