Memory design for vectorization

Vectorizing involves parallel access to data elements from a random access memory (RAM). However, a single memory module of conventional design can access no more than one word during each cycle of the memory clock. One common solution is to partition the memory into multiple modules or memory banks with address interleaving, leading to a number of disadvantages and restrictions over vectorizing. A different approach is to design memory modules with built-in access ability to commonly used array partitions. In this paper, a new memory organization is proposed, in which words can be formed row-wise, column-wise or diagonally at the control of an external input. The behavioural and structural representation of this design have been defined