A novel strained Si channel heterojunction PMOSFET based on MBE LT-Si technology

A novel MBE-grown method using low-temperature (LT) Si technology is introduced into the fabrication of strained Si channel heterojunction PMOSFETs. This technology reduces thickness of relaxed Si_1-xGe_x epitaxy layer from several micros using UHVCVD to less than 500nm, which improves the heat dissipation of devices. AFM tests of strained Si surface show RMS is less than 1nm and TD density less than 10⁶cm^-2 (TEM). The I-V measurements indicate that hole mobility mu_p has an enhancement of 25% compared to similarly processed bulk Si PMOSFET