A novel strained Si channel heterojunction PMOSFET based on MBE LT-Si technology

Author

Zhang, Jing ; Liu, Yu-kui ; Zhang, Zheng-fan ; Xu, Shi-liu ; He, Kai-quan ; Chen, Guang-bing ; Xu, Xue-liang ; Tan, Kai-zhou ; Xu, Wan-jing ; Yang, Mo-hua ; Li, Jing-chun ; Mei, Ding-lei ; Yu, Qi

Author_Institution

National Lab. of Analog Integrated Circuits, Chongqing

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

158

Lastpage

161

Abstract

A novel MBE-grown method using low-temperature (LT) Si technology is introduced into the fabrication of strained Si channel heterojunction PMOSFETs. This technology reduces thickness of relaxed Si_1-xGe_x epitaxy layer from several micros using UHVCVD to less than 500nm, which improves the heat dissipation of devices. AFM tests of strained Si surface show RMS is less than 1nm and TD density less than 10⁶cm^-2 (TEM). The I-V measurements indicate that hole mobility mu_p has an enhancement of 25% compared to similarly processed bulk Si PMOSFET

Keywords

CVD coatings; MOSFET; hole mobility; semiconductor technology; AFM tests; MBE LT technology; MBE-grown method; UHVCVD; heterojunction PMOSFET; hole mobility; low-temperature silicon technology; strained silicon channel; Capacitive sensors; Epitaxial growth; Fabrication; Germanium silicon alloys; Heterojunctions; Integrated circuit technology; MOSFET circuits; Molecular beam epitaxial growth; Oxidation; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306126

Filename

4098048